As discussed in the above-referenced '581 application, in order to accurately recover originally transmitted information signals that have been transported over a limited bandwidth dispersive channel, such as a copper telephone line, digital communication systems process successive samples of received signals through one or more signal processing operators, such as an adaptive transversal filter, which functions to reduce or minimize intersymbol interference (ISI) in the received signal path.
FIG. 1 diagrammatically shows a non-limiting example of a cascaded arrangement of a T-spaced feedforward linear transversal filter section 10 and a decision feedback (DFB) equalizer and data decision block 20, to which a received signal sample plus shaped noise (NEXT) is applied at the appropriate received timing epoch (i.e., symbol rate) derived by a timing epoch recovery subsystem. In accordance with current practice, the signal processing mechanism of interest is preferably implemented using digital components, so that the received signal is initially sampled and digitized by an analog-to-digital converter (ADC).
The feedforward linear filter section 10 typically comprises a delay line 12, each successive delay stage (z.sup.-1) of which stores a respective received sample (clocked at the symbol rate). Using a receiver clock signal derived from the timing signal recovery subsystem, such as a application specific integrated circuit (ASIC) digital phase locked loop (DPPL) 30, successive received samples provided over an input link 11 through automatic gain control amplifier circuitry 19 are clocked into and through the respective z.sup.-1 stages of the delay line 12.
As successive received signal samples are clocked through the delay line 12, the contents of its respective z.sup.-1 stages are multiplied in multipliers 13 by respective weighting coefficients W.sub.i and then summed in an accumulator 14, to produce a combined output for application to the decision feedback section 20, from the output of which data decision estimates are derived on output line 21. The output of the accumulator 14 is adjusted by subtracting the output of decision feedback section 20, as shown at subtraction operator 16. The effect of this subtraction is to remove intersymbol interference caused by the postcursors of the previously detected symbols.
The data decision estimates provided via output line 21 are derived on a symbol by symbol basis, by means of a symbol decision mechanism 22 (such as a slicer, which produces an estimate of the baud based on which region of spaced boundaries the received baud (at the output of a substraction operator 16) falls on. These output data decisions on output line 21 are then fed back to decision feedback equalizer 23, in order to remove intersymbol interference from future symbols.
Like the feedforward linear transversal filter section 10, decision feedback equalizer 23 also includes a delay line, the contents of respective stages of which are multiplied in respective multipliers by associated weighting coefficients and then summed in an accumulator to produce a combined output on link 24. As described above, this combined output 24 is subtracted in subtraction operator 16 from the output of accumulator 14 of the feedforward section 10.
In order to adjust the weighting coefficients for the feedforward linear transversal filter section 10 and the decision feedback section 23, a residual error signal may be obtained by differentially combining at 26 the data decision estimates at output 21 with the output of subtraction operator 16. This residual error signal is then coupled to a tap (weighting coefficient) update mechanism 40, which updates (recalculates) the respective weighting coefficients W.sub.i for multipliers 13, as well as the coefficients W1.sub.i of the decision feedback section 23.
In the cascaded linear equalizer--decision feedback equalizer arrangement of FIG. 1, in order to adjust the frequency and phase of the local receiver clock, so that it tracks the remote transmitter clock, the received clock recovery loop 30 is coupled to receive the error signal derived by a linear canceler section 50. Linear canceler section 50 functions as a predictor and is coupled to receive the successively received samples on received sample input link 11 and the symbol decision value estimates on link 21 as generated by symbol decision mechanism 22 of decision feedback section 20.
The linear canceler section 50 includes an alignment delay stage 51, to which successive received symbol samples on input link 11 are coupled, and the output of which is coupled to a subtraction operator 52. A multistage linear canceler section 53 consisting of a delay line and associated coefficients is coupled to receive the successive output symbol estimates on link 21, and provides signal estimates to the subtraction operator 52. The difference output of subtraction operator 52 is then used to update the coefficients employed by linear canceler section 53. In order to generate a timing error signal for adjusting the clock signal output by the received clock recovery loop 30, the ratio between the sampled signal value (A) associated with the cursor tap stage and that (B) of the first precursor tap stage of the linear canceler section 53 is calculated and compared with an offset value associated with the transmission line of interest.
Prior to calculating the ratio of the first precursor tap value to the cursor tap value, the cursor tap value on link 56 is normalized by a `scaling` gain stage 58. The offset value is typically predetermined (calculated) by conducting (laboratory) measurements upon the type of transmission line being used and storing a set of such values (associated with respectively different line lengths) in a look-up table. Once the equipment is installed, the receiver is programmed to use one of the offsets based on the value set by the automatic gain control amplifier circuitry 19.
In the ideal situation (no sample timing error), the precursor/cursor ratio (B/A) will match the expected offset value, indicating that the sampling clock is aligned with the peak of the received baud. However, in reality, due to master oscillator sensitivity to temperature gradients, it can be expected that the two will not match. This difference between successive precursor/cursor signal value ratios represents a timing error used by the timing recovery phase locked loop (PLL) 30 to adjust the recovered clock.
Where cost is not necessarily a major factor, such as in government-funded applications, the phase locked loop of the receiver's timing recovery subsystem may include a high precision voltage controlled oscillator and attendant parameter (e.g., temperature) variation compensation components, that are configured to enable the receiver's analog-to-digital converter to sample received signals at the optimum baud timing. In the commercial world, however, where competition dictates that cost be minimized without substantial loss in performance, the supplier of communication equipment does not have the luxury of increasing the complexity (and expense) of a given signal processing architecture, in order to achieve `the best of all possible worlds`.
Thus, there is a need to provide a signal processing mechanism for digital communication signal recovery, that effectively allows continued use of digital components to the extent possible, that facilitates ASIC implementation, yet provides sampling time correction and sampled signal interpolation as necessary to accommodate application parameters that can be expected to vary among different system installations.